The invention relates to technology for designing and verifying an integrated circuit (“IC”) design.
An IC has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer. The design of an integrated circuit transforms a circuit description into a geometric description called a layout. The process of converting specifications of an integrated circuit into a layout is called the physical design. After the layout is complete, it is then checked to ensure that it meets the design requirements. The result is a set of design files, which are then converted into pattern generator files. The pattern generator files are used to produce patterns called masks by an optical or electron beam pattern generator. Subsequently, during fabrication of the IC, these masks are used to pattern chips on the silicon wafer using a sequence of photolithographic steps. Electronic components of the IC are therefore formed on the wafer in accordance with the patterns.
Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language. An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction using a computer synthesis process. A netlist describes interconnections of nodes and components on the chip and includes information, for example, of circuit primitives such as transistors and diodes, their sizes and interconnections.
An integrated circuit designer may uses a set of layout EDA application programs to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes.
After an integrated circuit designer has created an initial integrated circuit layout, the integrated circuit designer then tests and optimizes the integrated circuit layout using a set of EDA testing and analysis tools. Common testing and optimization steps include extraction, verification, and compaction. The steps of extraction and verification are performed to ensure that the integrated circuit layout will perform as desired. The test of extraction is the process of analyzing the geometric layout and material composition of an integrated circuit layout in order to “extract” the electrical characteristics of the designed integrated circuit layout. The step of verification uses the extracted electrical characteristics to analyze the circuit design using circuit analysis tools.
Common electrical characteristics that are extracted from an integrated circuit layout include capacitance and resistance of the various “nets” (electrical interconnects) in the integrated circuit. These electrical characteristics are sometimes referred to as “parasitic” since these are electrical characteristics are not intended by the designer but result from the underlying physics of the integrated circuit design. For example, when an integrated circuit designer wishes to connect two different locations of an integrated circuit with an electrical conductor, the electrical circuit designer would ideally like perfect conductor with zero resistance and zero capacitance. However, the geometry of a real conductor, its material composition, and its interaction with other nearby circuit elements will create some parasitic resistance and parasitic capacitance. The parasitic resistance and parasitic capacitance affect the operation of the designed integrated circuit. Thus, the effect of the parasitic resistance and parasitic capacitance on the electrical interconnect must be considered.
To test an integrated circuit layout, the integrated circuit designer ‘extracts’ parasitic resistance and parasitic capacitance from the integrated circuit layout using an extraction application program. Then, the integrated circuit designer analyzes and possibly simulates the integrated circuit using the extracted parasitic resistance and parasitic capacitance information. If the parasitic resistance or parasitic capacitance causes undesired operation of the integrated circuit, then the layout of the integrated circuit must be changed to correct the undesired operation. Furthermore, minimizing the amount of parasitic resistance and parasitic capacitance can optimize the performance of the integrated circuit by reducing power consumption or increasing the operating speed of the integrated circuit.
Lithography simulation has recently gathered more attention in the past decades or two because of the increasing cost in manufacturing photomasks and development time to redesign and remanufacture a revised set of photomasks in case of an error in the design of the masks. A typical lithography system configuration is shown in FIG. 1 which comprises a light source 102, a lens 104, a photolithographic mask 106, a reduction lens 108, and the photo resist 110 on a wafer 112. There are three main steps in lithography simulation: optical simulation, photo mask modeling, and photo resist simulation. One of the main steps in lithography simulation is to simulate the propagation of light waves through a photo mask. The most accurate and robust approach to lithography simulation is to solve the Maxwell's equations using numerical techniques such as finite-difference time-domain (FDTD) or finite element method (FEM).
With the advance of deep submicron technologies, resolution enhancement techniques (RET) have become one of the most important techniques to guarantee design for manufacturability (DFM). Nonetheless, RET may pose further challenges to the integrated circuit (IC) design due to the continual pursuit for smaller geometry size and the use of shorter wavelength on the lithographic tools such as the 193 nm λ ultra-high numerical aperture (NA) lithography or even the Extreme Ultra Violet lithography, especially in the deep submicron and increasing clock frequency designs. For example, in order to meet the increasing demand for higher resolution and finer geometries, the semiconductor industry has been pushing in order to obtain larger numerical aperture (NA) to achieve smaller minimum feature size. However, larger numerical aperture also decreases the depth of focus, and such decreased depth of focus causes the lithographic tools' ability to print accurate circuits to be more sensitive to the topographical variation of the films on the wafer. This continual push towards smaller feature sizes and higher clock frequencies has made lithographic simulation even more important.
Experience indicates that even the state-of-the-art solvers are too slow or memory-bounded to handle a medium-size mask structure. As a result, a compact mask model is commonly used to obtain an approximate solution. A commonly used compact model is based on the Kirchhoff approximation or a thin mask model—if there is a mask opening, the light shines through it without any change in magnitude and phase; otherwise, the light is taken as completely blocked in the Kirchhoff model. This Kirchhoff approximation, however, neglects the effects such as diffraction, polarization, and coupling among various openings and features in the mask. On the other hand, the accuracy of the Kirchhoff approximation is reasonably good if two assumptions are satisfied. Firstly, the Kirchhoff approximation assumes that the thickness of the mask is sufficiently smaller than the wavelength of the incidence wave. The Kirchhoff approximation further assumes that the size of the openings is sufficiently larger than the wavelength of the incidence wave. Nonetheless, this is clearly not the case for phase-shifted masks. Moreover, these assumptions may no longer be true even for the binary mask for 45 nm or smaller technology nodes. It has been demonstrated that the Kirchhoff approximation, or the thin mask model, fails when the thickness of the mask is greater than the wavelength of the incidence wave of the lithographic equipment. It has also been demonstrated that the Kirchhoff approximation or the thin mask model fails to provide satisfactory solution when the size of the aperture is smaller than the wavelength of the incidence wave of the lithographic equipment.
Several attempts have been made to obtain a modified mask model or a modified Kirchhoff model to improve the accuracy. These attempts seek to tune the width of the aperture and/or the transmission coefficients to fit the far field generated by a more accurate solver. There are two commonly used approaches to generate such a modified mask model or modified Kirchhoff model. The first approach generally uses the boundary layer method which requires a 3D solver as the core engine and is thus CPU (central processing unit) intensive. The other commonly used approach uses the domain decomposition method which generally uses a 2D solver as the core engine but ignores the coupling between openings and features due to the domain decomposition and any mixing of different polarization components. Both methods produce the so-called modified thin-mask model. The key parameters in these models, the sizes and the transmission coefficients of the openings, are basically tuned to fit the far-field predicted by the modified thin-mask model to that predicted by the full field solver.
Nonetheless, most, if not all, of the approaches suffer from some major drawbacks. These modified thin-mask approaches are based directly or indirectly upon a heuristic parametric model which is derived from physical assumptions. The quality of the model then depends on the apriori assumptions. For example, an artificial rectangular aperture or an opening with a constant transmission coefficient across the aperture or opening is used to mimic the diffraction pattern on the wafer surface. Mathematically and practically, this is a multi-dimensional curve fitting process for some intrinsic parameters which include, for example, width and height of the rectangular aperture or opening, the constant transmission coefficient, the profile of the phase-shift mask, and a host of illumination parameters (e.g., on-axis or off-axis, shape and size of the source, etc.) The accuracy of such a curve-fitting process has been demonstrated to be unreliable. Moreover, in order to make this multi-dimensional curve fitting process tractable, most, if not all, of these modified thin-mask approaches considers only one aperture or opening at a time and do not account for coupling among various openings and features in the mask.
In addition, these multi- or high-dimensional piecewise constant curve fitting functions may be relatively simpler and efficient, but they may not be sufficiently accurate to meet the design requirements. For example, it is hard to account for effects such as diffraction, coupling, or polarization with these modified thin-mask models. One could use more sophisticated curve fitting techniques to improve the accuracy, but the high-dimensional curve fitting is typically not sufficiently robust or efficient. Hence these modified thin-mask models are typically limited only to small number of parameters in small mask structures.
That is, these modified thin-mask models are essentially a result of a multi-dimensional curve fitting process which is known to be numerically unreliable and CPU intensive. It is also very difficult to assert the accuracy of such modified thin-mask models, and hence the fidelity of the models is not guaranteed. More importantly, a few critical assumptions are made to simplify the form of the modified thin-mask model in order to make the curve fitting process tractable. As a consequence, many important effects, such as couplings among openings and features and polarization, are not well modeled in the modified thin-masks model. For more advanced technology nodes, when the feature size is 45 nm or below, the poor accuracy of such modified thin-mask or modified Kirchhoff models would render these models much less useful than they are at 65 nm or above technology nodes.
For technology nodes up to 65 nm, the mask feature sizes are almost always bigger than the wave length of lithography light sources of the photo lithographic equipment. The mask models in the Kirchhoff models may represent a reasonable compromise between accuracy and simulation speed. Nonetheless, starting from 45 nm technology nodes, the mask feature sizes become increasingly smaller than the wave length(s) of the lithographic equipment, and this continual shrinkage of the feature sizes has rendered the accuracy of the Kirchhoff mask models even more questionable.
Therefore, it is desirable to devise a method, system, and computer program product to better simulate the photolithography process with better accuracy and efficiency. More particularly, some embodiments achieve better accuracy by accommodating some or all relevant effects without having to solve the physics-based partial differential equations. Some embodiments maintains better efficiency by starting with a physics-based governing equation incorporating relevant effects while employing model reduction techniques to improve the efficiency.